The present invention relates to a semiconductor device having a high-impurity-concentration diffusion layer which is free from crystal defects.
In general, parasitic resistances in respective elements are regarded as one factor for degrading the performance of a device such as an IC or an LSI. For example, in a bipolar transistor, an emitter parasitic resistance r.sub.e, a base parasitic resistance r.sub.b, and a collector parasitic resistance r.sub.c are generated. Of these resistances, the collector parasitic resistance is most important. That is, since a transient response of a transistor and a large-current operation speed are often suppressed by the collector resistance, it is a key point of characteristic improvement of a bipolar transistor to decrease a collector saturation resistance (to be referred to as r.sub.sc hereinafter) measured in a state wherein the transistor is saturated.
FIG. 3A shows a conventional bipolar transistor, and FIG. 3B shows the bipolar transistor along a line IIIB--IIIB. The transistor is manufactured as will be described below. A high-impurity-concentration n-type buried collector layer 2 is formed on a p-type silicon substrate 1, an n-type epitaxial layer 3 is grown thereon, and a p-type base layer 4 and an n-type emitter layer 5 are sequentially formed. Reference numeral 6a denotes a high-impurity-concentration n-type diffusion layer for compensating a collector resistance; 7a and 8, polysilicon films; 9, an insulating isolation groove; and 10, an insulating film made of an SiO.sub.2 film or the like. Reference numerals 11a, 11b, and 11c denote collector, emitter, and base electrode extraction windows, respectively. The size of the collector electrode extraction window 11a is given by x.times.y in FIG. 3A. Note that an aluminum wiring and the like are omitted for descriptive convenience.
A collector parasitic resistance can be calculated by the resistances r.sub.1, r.sub.2, and r.sub.3 of the epitaxial layer 3, the buried collector layer 2, and the n-type diffusion layer 6a. The collector parasitic resistance is given as r.sub.c =r.sub.1 +r.sub.2 +r.sub.3. When the transistor is saturated, the resistance satisfies condition r.sub.sc =r.sub.1 +r.sub.2, and the resistance r.sub.3 is negligible. In this case, the resistance r.sub.1 is determined by a sheet resistance .rho..sub.1 of the diffusion layer and the pattern size thereof, and the resistance r.sub.2 is determined by a sheet resistance .rho..sub.1 of the buried collector layer and the pattern size thereof. As the sheet resistance .rho..sub.2 of the buried collector layer, a value of about 20 .OMEGA./.quadrature. can be stably obtained by a coating diffusion method or an ion implantation method generally using an arsenic glass film as a diffusion source. However, since the sheet resistance .rho..sub.1 is changed from several tens .OMEGA./.quadrature. to several k.OMEGA./.quadrature. depending on the type of method of doping an impurity, the saturation resistance r.sub.sc can be determined by the sheet resistance .rho..sub.1. In other words, the characteristics of the transistor depend on the sheet resistance .rho..sub.1.
It is important to dope a higher-concentration-impurity to decrease the sheet resistance .rho..sub.1. As a diffusion method, the following method is used as described in, e.g., Japanese Patent Laid-Open No. 57-10230. That is, a polysilicon film is left to cover an electrode window, and a collector contact layer is formed on a semiconductor surface through the polysilicon film. In FIGS. 3A and 3B, phosphorus P is doped in a polysilicon film 7a by thermal diffusion using a POCl.sub.3 vapor, and the phosphorus P is diffused from the polysilicon film 7a in an epitaxial layer 3 in an N.sub.2 gas. According to this method, variations in resistance of films in a wafer surface are small, and controllability in the direction of depth of the wafer is excellent. In addition, high-impurity-concentration phosphorus P can be advantageously doped by this method.
Therefore, even in the above conventional diffusion method, when an integration density is not high, a parasitic resistance can be suppressed to be less than a predetermined value even when the impurity concentration of the diffusion layer is about 10.sup.19 atoms/cm.sup.3. In recent years, as a high integration density has been demanded, a pattern size has been required to be minimized, and an area for a collector has been decreased accordingly. In order to cope with this, an impurity concentration must be increased to be about 10.sup.20 atoms/cm.sup.3 or more. For this reason, a conventional method cannot overcome this problem.
For example, in order to decrease the size of the transistor in FIG. 3, since a length x is determined by the length of an emitter electrode extraction window 11b, a length y must be decreased. Although even x.times.y =6.times.3 .mu.m.sup.2 is satisfactory in past, x.times.y=6.times.1.2 .mu.m.sup.2 must be satisfied at present. When a phosphorus concentration is increased to compensate this decrease, a yield of products is decreased. If the phosphorus concentration is increased up to a predetermined concentration, the yield of products is gradually decreased to almost zero.
This defect is electrically detected as junction leakage of a transistor. Crystal defects are mainly caused by leakage of the junction of bipolar transistors. When crystal defects were observed by a transmission electron microscope (TEM) in a defective product, dislocations were detected. The density of dislocations is highest in a phosphorus diffusion window and rapidly decreased in accordance with an increase in distance from the window. Several dislocations reach an emitter junction and a base junction. In short, since dislocations which occur from the phosphorus diffusion layer extend through the emitter and base junctions, junction leakage occurs.
As described above, since a yield of transistors is decreased depending on a phosphorus concentration, when the size of the window is set to be 6.0.times.1.2 .mu.m.sup.2 and a relationship between a peak phosphorus concentration and the number of dislocations reaching an emitter is inspected, the result in FIG. 4 can be obtained. As shown in FIG. 4, when the peak concentration is higher than 7.times.10.sup.19, the number of dislocations is rapidly increased.